In synchronous coherent RF receiver systems, a symbol clock must be generated for demodulation purposes. One conventional procedure for generating the symbol clock is to convert the IF (intermediate frequency) signal from analog to digital format, and then use digital signal processing algorithms to recover the symbol clock. This approach is typically referred to as software recovery. Another conventional approach is to use a phase locked loop (PLL) with a voltage controlled oscillator (VCO) and an analog loop filter. This latter approach is used in SONET systems.
The aforementioned software recovery approach utilizes digital processing resources on the baseband side, thereby disadvantageously increasing the total digital processing resources required by the receiver system. The aforementioned PLL approach requires additional components to realize the PLL, thereby disadvantageously increasing both the cost of the system and the amount of space (for example printed circuit board area) required.
It is therefore desirable to provide a symbol clock for demodulation in synchronous coherent RF receiver systems without the aforementioned disadvantages of conventional approaches.
According to the invention, a symbol clock associated with a symbol stream can be recovered by phase-adjusting a symbol clock signal to produce the symbol clock. The phase adjustment is accomplished by applying a digitally controlled delay to the symbol clock signal based on a timing relationship between the symbol clock and symbol transitions in the symbol stream.